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semiconductor group 1 10.98 hyb39s64400/800/160at(l) 64mbit synchronous dram 64 mbit synchronous dram the hyb39s64400/800/160at are four bank synchronous drams organized as 4 banks x 4mbit x4, 4 banks x 2mbit x8 and 4 banks x 1mbit x16 respectively. these synchronous devices achieve high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. the chip is fabricated with siemens advanced quarter micron 64mbit dram process technology. the device is designed to comply with all jedec standards set for synchronous dram products, both electrically and mechanically. all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate is possible depending on burst length, cas latency and speed grade of the device. auto refresh (cbr) and self refresh operation are supported. these devices operates with a single 3.3v +/- 0.3v power supply and are available in tsopii packages. the -8 version of this product is best suited for use on a 100 mhz bus for both cas latencies 2 & 3. ? high performance: ? fully synchronous to positive clock edge ? 0 to 70 c operating temperature ? four banks controlled by ba0 & ba1 ? programmable cas latency: 2 & 3 ? programmable wrap sequence: sequential or interleave ? programmable burst length: 1, 2, 4, 8 ? full page (optional) for sequential wrap around -8 -8b -10 units fck max. 125 100 100 mhz tck3 8 10 10 ns tac3667ns tck2 10 12 15 ns tac2678ns ? multiple burst read with single write operation ? automatic and controlled precharge command ? data mask for read / write control (x4, x8) ? data mask for byte control (x16) ? auto refresh (cbr) and self refresh ? suspend mode and power down mode ? 4096 refresh cycles / 64 ms ? random column address every clk ( 1-n rule) ? single 3.3v +/- 0.3v power supply ? lvttl interface version ? plastic packages: p-tsopii-54 400mil width (x4, x8, x16) ? -8 version for pc100 2-2-2 applications -8b version for pc100 3-2-3 applications
semiconductor group 2 hyb39s64400/800/160at(l) 64mbit synchronous dram ordering information pin description and pinouts: type ordering code package description lvttl-version: hyb 39s64400at-8 p-tsop-54-2 (400mil) 4b x 4m x 4 sdram pc100-222 hyb 39s64400at-8b p-tsop-54-2 (400mil) 4b x 4m x 4 sdram pc100-323 hyb 39s64400at-10 p-tsop-54-2 (400mil) 4b x 4m x 4 sdram pc66-222 hyb 39s64800at-8 p-tsop-54-2 (400mil) 4b x 2m x 8 sdram pc100-222 hyb 39s64800at-8b p-tsop-54-2 (400mil) 4b x 2m x 8 sdram pc100-323 hyb 39s64800at-10 p-tsop-54-2 (400mil) 4b x 2m x 8 sdram pc66-222 hyb 39s64160at-8 p-tsop-54-2 (400mil) 4b x 1m x 16 sdram pc100-222 hyb 39s64160at-8b p-tsop-54-2 (400mil) 4b x 1m x 16 sdram pc100-323 hyb 39s64160at-10 p-tsop-54-2 (400mil) 4b x 1m x 16 sdram pc66-222 hyb 39s64xxx0atl-8/-10 p-tsop-54-2 (400mil) low power (l-versions) clk clock input dq data input /output cke clock enable dqm, ldqm, udqm data mask cs chip select vdd power (+3.3v) ras row address strobe vss ground cas column address strobe vddq power for dqs (+ 3.3v) we write enable vssq ground for dqs a0-a11 address inputs nc not connected ba0, ba1 bank select
semiconductor group 3 hyb39s64400/800/160at(l) 64mbit synchronous dram pinout for x4, x8 & x16 organised 64m-sdrams vdd nc vddq nc dq0 vssq nc nc vddq nc dq1 vssq nc vdd nc we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 vdd vss nc vssq nc dq3 vddq nc nc vssq nc dq2 vddq nc vss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 18 19 20 21 22 23 24 25 26 27 vdd dq0 vddq nc dq1 vssq nc dq2 vddq nc dq3 vssq nc vdd nc we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 vdd vss dq7 vssq nc dq6 vddq nc dq5 vssq nc dq4 vddq nc vss nc dqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss vss dq15 vssq dq14 dq13 vddq dq12 dq11 vssq dq10 dq9 vddq dq8 vss nc udqm clk cke nc a11 a9 a8 a7 a6 a5 a4 vss vdd dq0 vddq dq1 dq2 vssq dq3 dq4 vddq dq5 dq6 vssq dq7 vdd ldqm we cas ras cs ba0 ba1 a10 a0 a1 a2 a3 vdd 16m x 4 8m x 8 4m x 16 tsopii-54 (10.16 mm x 22.22 mm, 0.8 mm pitch)
semiconductor group 4 hyb39s64400/800/160at(l) 64mbit synchronous dram block diagram for 4 bank x 4m x 4 sdram row decoder memory array bank 0 4096 x 1024 x 4 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096 x 1024 x 4 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096 x 1024 x 4 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096 x 1024 x 4 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq3 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a9, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqm row addresses column addresses
semiconductor group 5 hyb39s64400/800/160at(l) 64mbit synchronous dram block diagram for 4 banks x 2m x 8 sdram row decoder memory array bank 0 4096 x 512 x 8 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096 x 512 x 8 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096 x 512 x 8 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096 x 512 x 8 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq7 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a8, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqm row addresses column addresses
semiconductor group 6 hyb39s64400/800/160at(l) 64mbit synchronous dram block diagram for 4 banks x 1m x16 sdram row decoder memory array bank 0 4096x256 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096x256 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096x256 x16 bi t column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096x256 x16 bi t column decoder sense amplifier & i(o) bus input buffer output buffer dq0-dq15 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a7, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqmu dqml row addresses column addresses
semiconductor group 7 hyb39s64400/800/160at(l) 64mbit synchronous dram signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode, suspend mode, or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras , cas, we input pulse active low when sampled at the positive rising edge of the clock, cas , ras , and we define the command to be executed by the sdram. a0 - a11 input level during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organisation: 16m x 4 sdram can = ca9 (page length = 1024 bits) 8m x 8 sdram can = ca8 (page length = 512 bits) 4m x 16 sdram can = ca7 (page length = 256 bits) in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10 (=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will be precharged regardless of the state of ba0 and ba1. if a10 is low, then ba0 and ba1 are used to define which bank to precharge. ba0,ba1 input level bank select (bs) inputs. selects which bank is to be active. dqx input output level data input/output pins operate in the same manner as on conventional drams. dqm ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sampled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. one dqm input it present in x4 and x8 sdrams, ldqm and udqm controls the lower and upper bytes in x16 sdrams. vdd,vss supply power and ground for the input buffers and the core logic. vddq vssq supply isolated power supply and ground for the output buffers to provide improved noise immunity.
semiconductor group 8 hyb39s64400/800/160at(l) 64mbit synchronous dram operation definition all of sdram operations are defined by states of control signals cs , ras , cas , we , and dqm at the positive edge of the clock. the following list shows the truth table for the operation commands. note: 1. v = valid, x = dont care, l = low level, h = high level 2. cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. 3. this is the state of the banks designated by bs0, bs1 signals. 4. device state is full page burst operation 5. power down mode can not entry in the burst cycle. when this command assert in the burst mode cycle device is clock suspend mode. operation device state cke n-1 cke n cs ras cas we dqm a0-9, a11 a10 bs0 bs1 row activate (act) idle 3 h x l l h hxvvv read (read) active 3 hxlhlhxvlv read w/ autoprecharge (reada) active 3 hxlhlhxvhv write (write) active 3 hx lhl lxvlv write w/ autoprecharge (writea) active 3 hx lhl lxvhv row precharge (pre) any h x l l h l x x l v precharge all (prea) any h x l l h l x x h x mode register set (mrs) idle h x llll xvvv no operation (nop) anyh x l h h hxxxx device deselect (inhbt) anyh x h x x xxxxx auto refresh (refa) idle h h l l l hxxxx self refresh entry (refs-en)idle h l l l l hxxxx self refresh exit (refs-ex) idle (self refr.) lh hxxx xxxx lhhx power down entry (pdn-en) idle active 5 hl hxxx xxxx lhhx power down exit (pdn-ex) any (power down) lh hxxx xxxx lhhl data write/output enable active h xxxxxlxxx data write/output disable activehxxxxxhxxx
semiconductor group 9 hyb39s64400/800/160at(l) 64mbit synchronous dram address input for mode set (mode register operation) a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register (mx) cas latency m6 m5 m4 latency 000reserved 001reserved 010 2 011 3 100 reserved 101 110 111 burst length m2 m1 m0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 100 reserved reserved 101 110 1 1 1 full page *) burst type m3 type 0 sequential 1 interleave operation mode ba1 ba0 m11 m10 m9 m8 m7 mode 0000000 burst read / burst write 0000100 burst read / single write operation mode ba0 ba1 *) optional
semiconductor group 10 hyb39s64400/800/160at(l) 64mbit synchronous dram power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner.during power on, all vdd and vddq pins must be built up simultaneously to the specified voltage when the input signals are held in the nop state. the power on voltage must not exceed vdd+0.3v on any of the input pins or vdd supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 m s is required followed by a precharge of both banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is divided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cycle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a operation mode field to differentiate between normal operation (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate command after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in precharged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is required. low signals of ras , cas , and we at the positive edge of the clock activate the mode set operation. address input data at this timing defines parameters to be set as shown in the previous table. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the selected bank is activated and all of sense amplifiers associated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd , from the ras timing. we is used to define either a read (we = h) or a write (we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 143 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page, where full page is an optional feature in this device. column addresses are segmented by the burst length and serial data accesses are done within this boundary. the first column address to be accessed is supplied at the cas timing and the subsequent addresses are generated automatically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is 2, then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. full page burst operation is only possible using the sequential burst type and page length is a function of the i/o organisation and column addressing. full page burst operation do not self terminate once the burst length has been reached. in other words, unlike burst length of 2, 3 or 8, full page burst continues until it is terminated using another command.
semiconductor group 11 hyb39s64400/800/160at(l) 64mbit synchronous dram similar to the page mode of conventional drams, burst read or write accesses on any column address are possible once the ras cycle latches the sense amplifiers. the maximum tras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycle is supported. when the previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst length. an interrupt which accompanies an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be done between different pages. burst length and sequence : refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any refresh mode. an on-chip address counter increments the word and the bank addresses and no bank information is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is required between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 full page (optional) nnn cn, cn+1, cn+2,..... not supported
semiconductor group 12 hyb39s64400/800/160at(l) 64mbit synchronous dram the chip has an on-chip timer and the self refresh mode is available. it enters the mode when ras , cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high enables the clock and initiates the refresh exit operation. after the exit command, at least one trc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ?high at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is activated, the write operation at the next clock is prohibited (dqm write mask latency t dqw = zero clocks). suspend mode during normal access mode, cke is held high enabling the clock. when cke is low, it freezes the internal clock and extends data read and write operations. one clock delay is required for mode entry and exit (clock suspend latency t csl ). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver circuits except clk and cke are gated off. the power down mode does not perform any refresh operations, therefore the device cant remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by taking cke ?high. one clock delay is required for mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock before the last data out for cas latencies 2 and two clocks for cas latencies 3. if cas10 is high when a write command is issued, the write with auto-precharge function is initiated. the sdram automatically enters the precharge operation a time delay equal to t wr (write recovery time) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2 and two clocks before the last data out for cas latency = 3. writes require a time delay twr from the last data out to apply the precharge command.
semiconductor group 13 hyb39s64400/800/160at(l) 64mbit synchronous dram bank selection by address bits : burst termination once a burst read or write operation has been initiated, there are several methods in which to terminate the burst operation prematurely. these methods include using another read or write command to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop command to terminate the existing burst operation but leave the bank open for future read or write commands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid dq contention. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the dq pins before the burst stop command is registered will be written to the memory. a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1 x x all banks
semiconductor group 14 hyb39s64400/800/160at(l) 64mbit synchronous dram absolute maximum ratings operating temperature range .........................................................................................0 to + 70 c storage temperature range...................................................................................... C 55 to + 150 c input/output voltage .............................................................................................C 0.3 to vdd+0 .3 v power supply voltage vdd / vddq.......................................................................... C 0.3 to + 4.6 v power dissipation............................................. ............................................................... ...........1 w data out current (short circuit) ............................................................................................... . 50 ma note: stresses above those listed under absolute maximum ratings may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. recommended operation and characteristics for lv-ttl versions: t a = 0 to 70 c; v ss = 0 v; v dd, v ddq = 3.3 v 0.3 v notes: 1. all voltages are referenced to vss. 2. vih may overshoot to vdd + 2.0 v for pulse width of < 4ns with 3.3v. vil may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. capacitance t a = 0 to 70 c; v dd = 3.3 v 0.3 v, f = 1 mhz parameter symbol limit values unit notes min. max. input high voltage v i h 2.0 vdd+0.3 v 1, 2 input low voltage v i l C 0.3 0.8 v 1, 2 output high voltage ( i out = C 4.0 ma) v oh 2.4 C v output low voltage ( i out = 4.0 ma) v ol C0.4v input leakage current, any input (0 v < v i n < vddq, all other inputs = 0 v) i i (l) C 5 5 m a output leakage current (dq is disabled, 0 v < v out < vdd ) i o(l) C 5 5 m a parameter symbol values unit min. max. input capacitance (clk) c i 1 2.5 4.0 pf input capacitance (a0-a12, ba0,ba1,ras , cas , we , cs , cke, dqm) c i 2 2.5 5.0 pf input / output capacitance (dq) c i o 4.0 6.5 pf
semiconductor group 15 hyb39s64400/800/160at(l) 64mbit synchronous dram operating currents (t a = 0 to 70 o c, vdd = 3.3v 0.3v (recommended operating conditions unless otherwise noted) notes: 3. these parameters depend on the cycle rate. these values are measured at 100 mhz for -8 and at 66 mhz for -10 parts. input signals are changed once during tck, excepts for icc6 and for standby currents when tck=infinity. 4. these parameters are measured with continuous data stream during read access and all dq toggling. cl=3 and bl=4 is assumed and the vddq current is excluded. parameter & test condition symb. -8/-8b -10 note max. operating current trc=trcmin., tck=tckmin. ouputs open, burst length = 4, cl=3 all banks operated in random access, all banks operated in ping-pong manner to maximize gapless data access icc1 x4 x8 x16 100 110 130 70 75 90 ma ma ma 3 precharge standby current in power down mode cs =vih (min.), cke<=vil(max) tck = min. icc2p 22 ma3 tck = infinity icc2ps 11ma3 precharge standby current in non-power down mode cs = vih (min.), cke>=vih(min) tck = min. icc2n 35 30 ma 3 tck = infinity icc2ns 55ma3 no operating current tck = min., cs = vih(min), active state ( max. 4 banks) cke>=vih(min.) icc3n 45 40 ma 3 cke<=vil(max.) icc3p 88ma3 burst operating current tck = min., read command cycling icc4 x4 x8 x16 60 70 100 40 50 70 ma ma ma 3,4 auto refresh current tck = min., auto refresh command cycling icc5 130 90 ma 3 self refresh current self refresh mode, cke=0.2v standard version icc6 11ma3 l-version 500 500 m a3
semiconductor group 16 hyb39s64400/800/160at(l) 64mbit synchronous dram ac characteristics 1)2) t a = 0 to 70 c; v ss = 0 v; vdd = 3.3 v 0.3 v, t t = 1 ns parameter symbol limit values unit -8 -8b -10 min. max. min. max. min. max. clock and clock enable clock cycle time cas latency = 3 cas latency = 2 t ck 8 10 C C 10 12 C C 10 15 C C ns ns clock frequency cas latency = 3 cas latency = 2 t ck C C 125 100 C C 100 83 C C 100 66 mhz mhz access time from clock cas latency = 3 cas latency = 2 t ac C C 6 6 6 7 C C 7 8 ns ns 2, 3 clock high pulse width t ch 3C3C3Cns clock low pulse width t cl 3C3C3Cns transition time t t 0.5 10 0.5 10 0.5 10 ns setup and hold times input setup time t is 2C2C2.5Cns 4 input hold time t ih 1C1C1Cns 4 cke setup time t cks 2C2C2.5Cns 4 cke hold time t ckh 1C1C1Cns 4 mode register set-up time t rsc 16C20C20Cns power down mode entry time t sb 08010010ns common parameters row to column delay time t rcd 20C20C30Cns 5 row precharge time t rp 20C30C30Cns 5 row active time t ras 50 100k 60 100k 60 100k ns 5 row cycle time t rc 70 C 80C90 C ns 5 activate(a) to activate(b) command period t rrd 16C20C20Cns 5 cas (a) to cas (b) command period t ccd 1C1C1Cclk
semiconductor group 17 hyb39s64400/800/160at(l) 64mbit synchronous dram refresh cycle refresh period (4096 cycles) t ref C64C64C64ms self refresh exit time t srex 10C10C10Cns read cycle data out hold time t oh 3C3C3Cns2 data out to low impedance time t lz 0C0C0Cns data out to high impedance time t hz 38310310ns dqm data out disable latency t dqz C2C2C2clk write cycle data input to precharge (write recovery) t wr 2C2C2Cclk dqm write mask latency t dqw 0C0C0Cclk parameter symbol limit values unit -8 -8b -10 min. max. min. max. min. max.
semiconductor group 18 hyb39s64400/800/160at(l) 64mbit synchronous dram notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests for lv-ttl versions have v il = 0.4 v and v ih = 2.4 v with the timing referenced to the 1.5 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t =1ns with the ac output load circuit shown in fig.1. specified tac and toh parameters are measured with a 50 pf only, without any resistive termination and with a input signal of 1v / ns edge rate between 0.8v and 2.0 v.. 3. if clock rising time is longer than 1 ns, a time (t t /2 - 0.5) ns has to be added to this parameter. 4. if tt is longer than 1 ns, a time (t t -1) ns has to be added to this parameter. 5. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 1.5v 1.5v tsetup thold tac tac tlz toh thz clock input output 50 pf i/o z=50 ohm + 1.5 v 50 ohm 2.4 v 0.4 v t t fig.1 tch tcl 50 pf i/o measurement conditions for tac and toh
semiconductor group 19 hyb39s64400/800/160at(l) 64mbit synchronous dram package outlines 1) does not include plastic or metal protrusion of 0.15 max. per side 54x 0.2 m - 0 . 03 -0.1 -0.2 0.6 0.1 1) index marking 0.15 max. 1 1.2 max. 27 1 28 54 + 0 . 0 6 0 . 1 5 +0.05 0.4 0.8 22.38 0.05 - + 0.2 - + 0.13 - + 5 max. o -0.25 10.16 tsopii-54 ( 400 mil ) tsop54-2.drw 11.76 plastic package p-tsopii-54 ( 400mil, 0.8mm lead pitch) thin small outline package, smd
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 20 timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1 read to write interval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. burst termination 8.1 termination of a full page burst write operation 8.2 termination of a full page burst write operation 9. ac- parameters 9.1 ac parameters for a write timing 9.2 ac parameters for a read timing 10. mode register set 11. power on sequence and auto refresh (cbr) 12. clock suspension (using cke) 12. 1 clock suspension during burst read cas latency = 2 12. 2 clock suspension during burst read cas latency = 3 12. 3 clock suspension during burst write cas latency = 2 12. 4 clock suspension during burst write cas latency = 3 13. power down mode and clock suspend 14. self refresh ( entry and exit ) 15. auto refresh ( cbr ) 16. random column read ( page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 17. random column write ( page within same bank) 17.1 cas latency = 2 17.2 cas latency = 3
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 21 timing diagrams (contd) 18. random row read ( interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 19. random row write ( interleaving banks) with precharge 19.1 cas latency = 2 19.2 cas latency = 3 20. full page read cycle 20.1 cas latency = 2 20.2 cas latency = 3 21. full page write cycle 21.1 cas latency = 2 21.2 cas latency = 3 22. precharge termination of a burst 22.1 cas latency = 2 22.2 cas latency = 3
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 22 1. bank activate command cycle (cas latency = 3) 2. burst read operation (burst length = 4, cas latency = 2, 3) address clk t0 t t1 t ttt command nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate t rcd : h or l t rc precharge t rrd bank b row addr. command read a nop nop nop nop nop nop nop t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 23 3. read interrupted by a read (burst length = 4, cas latency = 2, 3) 4.1 read to write interval (burst length = 4, cas latency = 3) command read a read b nop nop nop nop nop nop t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 command nop read a nop nop nop nop write b nop nop dqm dout a 0 din b 0 din b 1 din b 2 : h or l must be hi-z before the write command dqs minimum delay between the read and write commands = 4+1 = 5 cycles clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t dqz t dqw
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 24 4 2. minimum read to write interval (burst length = 4, cas latency = 2) 4. 3. non-minimum read to write interval (burst length = 4, cas latency = 2, 3 command nop bank a nop read a write a nop nop nop dqm : h or l din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command t ck2, dqs cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop activate 1 clk interval t dqz t dqw nop read a nop nop read a nop write b nop nop dqm din b 0 din b 1 din b 2 : h or l t ck2, dqs cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 1 dout a 0 dout a 0 din b 0 din b 1 din b 2 command must be hi-z before the write command t ck3, dqs cas latency = 3 t dqz t dqw
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 25 5. burst write operation (burst length = 4, cas latency = 2, 3) 6.1 write interrupted by a write (burst length = 4, cas latency = 2, 3) command nop write a nop nop nop nop nop nop dqs din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is ignored after the first data element and the write are registered on the same clock edge. dont care termination of a burst. command nop write a write b nop nop nop nop nop dqs din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 1 clk interval
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 26 6.2 write interrupted by a read (burst length = 4, cas latency = 2, 3 7.1 burst write with auto-precharge burst length = 2, cas latency = 2, 3) c ommand nop write a read b nop nop nop nop nop nop t ck2, dqs cas latency = 2 din a 0 t ck3, dqs cas latency = 3 din a 0 c lk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is ignored. input data must be removed from the dqs at least one clock cycle before the read data appears on the outputs to avoid data contention. dont care dont care dont care dout b 0 dout b 1 dout b 2 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 command nop nop nop write a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop bank a active nop nop din a 0 din a 1 * dqs begin autoprecharge bank can be reactivated after trp t wr t rp nop
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 27 7.2 burst read with auto-precharge (burst length = 4, cas latency = 2, 3) command read a nop nop nop nop nop nop nop t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 with ap begin autoprecharge bank can be reactivated after trp * * * t rp t rp t rp
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 28 8.1 termination of a full page burst read operation (cas latency = 2, 3) 8.2 termination of a full page burst write operation (cas latency = 2, 3) command read a nop nop nop burst nop nop nop nop t ck2, dqs cas latency = 2 t ck3, dqs cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 the burst ends after a delay equal to the cas latency. dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. dqs cas latency = 2,3,4 dont care
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 29 \ clk cke cs dq ras cas we bs dqm 9.1 ac parameters for write timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr t cks t cs t ch t ckh t as t rcd t rc t rp t ds activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ch t cl begin auto precharge bank a begin auto precharge bank b t wr t rrd activate command bank b ray cbx ray ray rbx rbx cax rby rby raz raz rax rax t ah
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 30 \ clk cke cs dq ras cas we bs dqm 9.2 ac parameters for read timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z ap burst length = 2, cas latency = 2 addr t cs t ch t ckh t as t ah t rrd t rcd t ras t lz activate command bank a activate command bank b activate command bank a precharge command bank a t cks t ck2 ax0 ax1 read with auto precharge command bank b t rc t rp t ac2 t ac2 t oh t hz t ch t cl bx0 begin auto precharge bank b bx1 t hz rbx ray rbx rbx ray cax rax rax read with auto precharge command bank a begin auto precharge bank a
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 31 \ clk cke cs ras cas we bs0,bs1 10. mode register set t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 a10,a11 a0-a9 precharge command all banks mode register set command any command address key cas latency = 2 t rsc
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 32 \ clk cke cs dq ras cas we bs dqm 11. power on sequence and auto refresh (cbr) ttt t0 tt t tt t t t tt t1 tttt tt tt hi-z ap addr precharge command all banks t rp minimum of 8 refresh cycles are required 1st auto refresh command t rc high level is required 8th auto refresh command inputs must be stable for 200 m s any command 2 clock min. mode register address key set command
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 33 \ clk cke cs dq ras cas we bs dqm 12.1 clock suspension during burst read (using cke) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr cax rax ax0 ax1 ax2 ax3 activate command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank a t hz t ck2 t csl t csl t csl
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 34 \ clk cke cs dq ras cas we bs dqm 12.2 clock suspension during burst read (using cke) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr rax ax0 ax1 ax2 ax3 activate command bank a clock suspend 2 cycles clock suspend 1 cycle clock suspend 3 cycles rax read command bank a cax t hz t ck3 t csl t csl t csl
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 35 \ clk cke cs dq ras cas we bs dqm 12.3 clock suspension during burst write (using cke) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr cax rax activate command bank a rax dax0 clock suspend 1 cycle dax1 dax2 dax3 clock suspend 2 cycles clock suspend 3 cycles write command bank a t ck2
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 36 \ clk cke cs dq ras cas we bs dqm 12.4 clock suspension during burst write (using cke) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr rax activate command bank a rax cax dax0 clock suspend 1 cycle dax1 dax2 dax3 clock suspend 2 cycles clock suspend 3 cycles write command bank a t ck3
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 37 \ clk cke cs dq ras cas we bs dqm 13. power down mode and clock suspend t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr t cks t cks cax rax rax ax2 ax0 ax1 ax3 activate command bank a clock suspend mode entry clock suspend mode exit read command bank a clock mask start clock mask end precharge command bank a power down mode entry power down mode exit t hz any command t ck2 active standby precharge standby
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 38 \ clk cke cs dq ras cas we dqm 14. self refresh (entry and exit) t2 t3 t4 t0 t1 t t tt t5 t t tt t t t tt tt t t hi-z ap all banks must be idle self refresh entry begin self refresh exit command t srex self refresh exit command issued self refresh exit t rc t cks any command bs addr t cks
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 39 \ clk cke cs dq ras cas we bs dqm 15. auto refresh (cbr) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr ax0 ax1 burst length = 4, cas latency = 2 activate command read command precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks cax rax rax bank a bank a ax2 ax3 (minimum interval)
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 40 \ clk cke cs dq ras cas we bs dqm 16.1 random column read (page within same bank) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck2
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 41 \ clk cke cs dq ras cas we bs dqm 16.2 random column read (page within same bank) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 42 \ clk cke cs dq ras cas we bs dqm 17.1 random column write (page within same bank) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck2 activate command bank b cax write command bank b raw raw activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 43 clk cke cs dq ras cas we bs dqm 17.2 random column write (page within same bank) t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 3 addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 44 clk cke cs dq ras cas we bs dqm 18.1 random row read (interleaving banks) with precharge t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 8, cas latency = 2 addr cby read command bank b read command bank a bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 t ck2 high t rcd t ac2 t rp cax precharge command bank b ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 45 clk cke cs dq ras cas we bs dqm 18.2 random row read (interleaving banks) with precharge t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 8, cas latency = 3 addr cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 46 clk cke cs dq ras cas we bs dqm 19.1 random row write (interleaving banks) with precharge t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 8, cas latency = 2 addr t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t wr write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t wr
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 47 clk cke cs dq ras cas we bs dqm 19.2 random row write (interleaving banks) with precharge t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 8, cas latency = 3 addr t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank a rax rax activate command bank b rbx rbx activate command bank a ray ray day3 t wr cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t wr t rcd
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 48 \ clk cke cs dq ras cas we bs dqm 20.1 full page read cycle t2 t3 t4 t0 t1 t6 t tt t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 2 addr t ck2 high ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 ax+1 bx+6 cbx read command bank b precharge command bank b burst stop command cax read command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby t rp full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. bursting beginning with the starting address.
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 49 \ clk cke cs dq ras cas we bs dqm 20.2 full page read cycle t2 t3 t4 t0 t1 t6 t7 t8 t t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 3 addr t ck3 high ax ax+1 ax-1 ax-2 ax+2 ax bx bx+1 bx+5 bx+4 bx+3 bx+2 ax+1 cbx read command bank b precharge command bank b burst stop command cax read command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby t rrd full page burst operation does not the burst counter wraps from the highest order page address back to zero durin g this time interval. terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address.
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 50 \ clk cke cs dq ras cas we bs dqm 21.1 full page write cycle t2 t3 t4 t0 t1 t t tt t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 2 addr t ck2 high cbx write command bank b precharge command bank b burst stop command cax write command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby data is ignored. dax dax+1 dax-1 dax+3 dax+2 dax dbx dbx+1 dax+1 dbx+3 dbx+2 dbx+4 dbx+5 dbx+6 full page burst operation does not terminate when the burst length is satisfied; the burst counter increments and continues the burst counter wraps from the highest order page address back to zero during this time interval. burstin g be g innin g with the startin g address.
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 51 \ clk cke cs dq ras cas we bs dqm 21.2 full page write cycle t2 t3 t4 t0 t1 t6 t tt t5 t t tt t tttt tt tt hi-z ap burst length = full page, cas latency = 3 addr t ck3 high cbx write command bank b precharge command bank b burst stop command cax write command bank a activate command bank a rax rax activate command bank b rbx rbx activate command bank b rby rby dax dax+1 dax-1 dax+3 dax+2 dax dbx dbx+1 dax+1 dbx+3 dbx+2 dbx+4 dbx+5 full page burst operation does not the burst counter wraps from the highest order page address back to zero during this time interval. terminate when the length is satisfied; the burst counter increments and continues bursting beginning with the starting address. data is ignored.
hyb39s64400/800/160at(l) 64mbit synchronous dram semiconductor group 52 \ clk cke cs dq ras cas we bs dqm 22.1 precharge termination of a burst t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 8 or full page, c a s latency = 2 addr t ck2 precharge command bank a dax0 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz caz read command bank a az0 az1 az2 precharge command bank a t rp
semiconductor group 20 10.98 hyb39s64400/800/160at(l) 64mbit synchronous dram change list: rev. 10.98 icc6 for l-version changed from 400 m a to 500 m a

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